The present invention relates to a semiconductor integrated circuit device and to a technique for the manufacture, thereof and, more particularly, the invention relates to a technique which is effective for application to a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
Memory cells of a DRAM are respectively placed at points where a plurality of word lines and a plurality of bit lines, disposed over a principal or main surface of a semiconductor substrate intersect in matrix form. The memory cell comprises one memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) and one information capacitive element (capacitor) electrically connected in series with the memory cell selection MISFET.
The memory cell selection MISFET is formed in an active region whose periphery is surrounded by a device separation region The memory cell selection MISFET is composed principally of a gate oxide film, a gate electrode formed integrally with each word line, and a pair of semiconductor regions which form a source and a drain. Each bit line is placed above the memory cell selection MISFET and is electrically connected to one of the source and drain shared by two memory cell selection MISFETs disposed adjacent to each other in its extending direction. Similarly, the information storage capacitive element is disposed above the memory cell selection MISFET and is electrically connected to the other of the source and drain.
Japanese Patent Application Laid-Open No. Hei 7-7084 discloses a DRAM of a capacitor over bitline (COB) structure wherein information storage capacitive elements are placed over the bit lines. According to the DRAM described in the publication, a lower electrode (storage electrode) of each information storage capacitive element disposed above the bit line is processed into cylindrical form to make up for a reduction in the amount of an electrical charge stored in each information storage capacitive element with macro-fabrication of each memory cell, whereby the surface area thereof is increased, and a capacitive insulating film and an upper electrode (plate electrode) are formed over the lower electrode.
According to the DRAM described in the publication as well, a frame-shaped groove (channel), which surrounds a memory array, is defined in the boundary between the memory array and a peripheral circuit region, and a thick insulating film is deposited over the peripheral circuit region outside the channel, whereby a step-like offset between the memory array and the peripheral circuit is settled and the flattening of the peripheral circuit region is implemented together. The groove is defined simultaneously in a process step for processing the lower electrode of each information storage capacitive element into cylindrical form. An inner wall of the groove is composed of the same material (polycrystal silicon film) as the lower electrode.